Superconductive crossbar switch

ABSTRACT

A superconductor crossbar switch for connecting a plurality of inputs with a plurality of outputs, including a switching cell having an input, an output and a circuit for connecting the input with the output for bidirectionally transmitting data therebetween. The connection of the retaining and releasing circuitry of a plurality of cells enables the switch to simultaneously retain a selected cell or cells of a group of cells and disable the remaining cells of that group, whereby a subsequent query on a disabled cell is inoperative until the selected cell or cells is released. The crossbar switch is characterized by latency on the order of nanoseconds, a data rate per channel on the order of gigabits per second, essentially zero crosstalk, and detection of contention in nanoseconds or less and resolution of contention in nanoseconds or less.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.11/209,662, filed on Aug. 24, 2005. U.S. application Ser. No. 10/200,115is a continuation of U.S. application Ser. No. 10/200,115, filed on Jul.23, 2002, now U.S. Pat. No. 6,960,929, issued Nov. 1, 2005, which, inturn, is based on and derives the benefit of U.S. Provisional PatentApplication Ser. No. 60/306,880, filed on Jul. 23, 2001. The entirety ofall of the above-listed Applications are incorporated herein byreference.

This invention was made with government support of Job No. 768, of theNational Security Agency. The government may have certain rights in thisinvention.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to superconductive switching devices, andin particular to a superconducting crossbar switch for bi-directionallyconnecting a plurality of inputs with a plurality of outputs.

2. Background of the Technology

Advances in high performance computing are being pursued in manydifferent directions. The technology thrust has been directed towardvery high speed, high circuit density chips which are of low power (topermit small volume packaging) and organized into a small number ofprocessors. Another thrust involves the use of many processors, tens toperhaps thousands, working in concert to perform the computation. Inthis case, the stress on the individual elements is relieved and thereis greater computational power, but interconnection problems that arisewith the added software complexity must be solved.

One of the configurations for a massively parallel computing systemcalls for a large number of processors to be connected to a large sharedmemory system on an equal access basis. The demands placed upon theinterconnection switch are formidable, in terms of complexity, speed,and intelligence. For example, the switch must have a short latency timeand must establish the requested connection very quickly, ideally withina small fraction of the processor clock time. The data rate per channelmust also be very high. For example, for a 32 bit word machine with a 30nanosecond clock, a data rate of 109 bits/second (i.e., gigabits/second)per processor is required. Once established, the data path must beimmune to noise, and crosstalk must be kept to a minimum. Theestablished link must be inviolate during the processor transaction timeand releasable very quickly, ideally within a clock cycle. There is aneed to inform the processor of successful connection. The time duringwhich two or more processors contend for the same memory port needs tobe minimized with fast resolution of these contentions. Finally, dataneeds to be transferred in both directions. Although there are a numberof switch architecture solutions, it is generally accepted that the bestsolution is a crossbar, which is a switch that allows the requestersequal access at the same level to any output line.

Computer systems also need high bandwidth and short access times tocarry out data exchange between memory and processors, and amongprocessors.

2. Related Art

Crossbar switches are well-known in the prior art, as evidenced by U.S.Pat. No. 3,539,730 to Imamura, which discloses a crossbar switch used ina two-stage link connection system. Each switch is divided into twoparts, in accordance with vertical groups. The parts of the switch areassigned to primary and secondary lattices, respectively, with linksbetween the lattices being formed by connecting the outgoing lines fromthe primary lattice of one switch with the secondary lattice of anotherswitch.

Also known in the art are polarity switching circuits which utilizeJosephson junction devices (e.g., interferometers) and superconductinginterconnections coupled to a utilization circuit, including one or morememory cells or logic circuits. Such circuits are disclosed, forexample, in U.S. Pat. No. 4,210,921 to Faris.

Prior switching circuits possess certain inherent drawbacks that renderthem unsuitable for use with large numbers of computing elements. As aresult, they cannot meet all of the requirements set forth above for amassively parallel computing system.

SUMMARY OF THE INVENTION

The present invention overcomes the above identified drawbacks of theprior switching circuits, as well as others, by providing a modularcrossbar switch that is extendable in size, operates under low powerwith low latency, and detects and resolves conflicts that arise when twoor more processors contend for the same memory port. The switch of thepresent invention is capable of interconnecting N computers orprocessors with M memories, or other processors or computers where N andM can be of the order of 1000 or more. One embodiment of the presentinvention is also modular, in that small crossbars can easily beextended to become very large ones, (e.g., 32×32 can grow into1000×1000). In addition, if the computer data rate exceeds that of onechannel, paralleling of channels is easily performed. The switch is alsosuitable for general communications network usage, as well.

An embodiment of the present invention includes a crossbar switch forconnecting a plurality of input devices with a plurality of outputdevices, and a switching cell having an input, an output, and anapparatus for connecting the output for bi-directionally transmittingdata there between. The connecting apparatus includes a superconductivedevice having zero resistance and negligible crosstalk, and a controldevice to control operation of the connecting apparatus. The connectingapparatus provides a connection for a plurality of processors orfunctional units to be connected to one another. For example, aconfiguration of adders, multipliers, and dividers can be switched, suchthat data can be routed sequentially from one function to another witharbitrary freedom.

Another embodiment of the present invention includes a secondsuperconductive device and a second control device to retain and releasethe operation of the first superconductive device.

An additional embodiment of the present invention includes a pluralityof inputs, a plurality of outputs, and a plurality of cells arranged ina matrix, with the inputs coupled to one plurality of cells and theoutputs connected to another plurality of cells, so as to define asuperconducting device matrix. In an embodiment of the presentinvention, the cells are connected in parallel with the inputs andoutputs.

In a further embodiment of the present invention, each output includes asumming device for summing output voltages or currents of the cellsconnected therewith, in order to accommodate the inputs and to renderthe matrix extendable in numbers of inputs and outputs. The summingdevice may include a summing amplifier or an additional superconductivedevice. In another embodiment of the present invention, the switchingcells include a feedback mechanism connected to the outputs which feedsdata to the outputs and acknowledges pulses back to a requester.

In yet another embodiment of the present invention, retaining andreleasing devices for the cells are connected to the outputs and areinterconnected and operable to simultaneously retain a selected cell ofthe plurality of cells, and disable the remaining cells of the pluralityof cells, whereby a subsequent query on a disabled cell is inoperativeuntil the selected cell is released. The crossbar also allows multicastor broadcast operation wherein any one input may be connectedsimultaneously or in arbitrary order to more than one or all of theoutput ports.

In a further embodiment of the invention, a sensing apparatus isconnected with each of the outputs for detecting simultaneous queries tocells of the respective groups of cells and for generating to theprocessors via the cells an indication of conflict from the simultaneousqueries as well as resolving these conflicts while preventing furtherinterference.

Additional advantages and novel features of the invention will be setforth in part in the description that follows, and in part will becomemore apparent to those skilled in the art upon examination of thefollowing or upon learning by practice of the invention.

BRIEF DESCRIPTION OF THE FIGURES

In the drawings:

FIG. 1 illustrates a prior art Josephson junction device;

FIG. 2 is a graph illustrating the operation of the Josephson junctiondevice of FIG. 1;

FIG. 3 is a simplified perspective view of a prior art Josephsonjunction device with a magnetic field control line;

FIG. 4 shows prior art operation of Josephson junctions in which aresistor is placed between the electrode and the counter-electrode forthe device shown in FIG. 1;

FIG. 5 is a schematic representation of a prior art SuperconductingQuantum Interference Device (SQUID) device;

FIG. 6 is a graph representing the operation of the SQUID device of FIG.5;

FIG. 7 illustrates a matrix of cells comprising a superconductivecrossbar switch, in accordance with an embodiment of the presentinvention;

FIGS. 8 and 9 illustrate use of the superconductive crossbar switch, inaccordance with an embodiment of the present invention;

FIGS. 10 and 11 illustrate use of the superconductive crossbar switch,connected to a summing device, in accordance with an embodiment of thepresent invention;

FIG. 12 is a schematic representation of a switch illustrating aplurality of summing devices, and the clamping and crossbar cell memorycircuit, in accordance with an embodiment of the present invention;

FIG. 13 is a schematic representation of the cell circuits and clampcircuit and their operation in the situation of no contention, inaccordance with an embodiment of the present invention;

FIG. 14 is a flow diagram illustrating operation of the circuits of FIG.12, in accordance with an embodiment of the present invention;

FIG. 15 is a timing diagram illustrating the operation of the circuitsof FIG. 13, and a situation of non-simultaneous request (no contention)for a memory line, in accordance with an embodiment of the presentinvention;

FIG. 16 is a schematic representation of the cell circuits in thesituation of two simultaneous requests for the same memory line, inaccordance with an embodiment of the present invention;

FIG. 17 is a timing diagram illustrating the operation of two processorscontending for the same output line, in accordance with an embodiment ofthe present invention;

FIG. 18 illustrates a representative physical layout of a 128×128crossbar switch, in accordance with an embodiment of the presentinvention; and

FIG. 19 illustrates a representation of a crossbar switch chip,including separate decoders and the switching matrix, in accordance withan embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 illustrates a Josephson tunnel junction device known in the priorart. The Josephson tunnel junction device includes top and bottom layers20, 21 of superconductor material sandwiching a thin insulating film 22.If a voltage V is applied between the top and bottom layers through aresistance R, there is a range of current in which zero resistancecurrent up to Im, can be transported between the two elements.

FIG. 2 illustrates the behavior of the circuit current I as the inputvoltage V is increased for a representative resistance R, in theJosephson tunnel junction device shown in FIG. 1. The voltage Vj acrossthe device will be zero until the device current exceeds Im, at whichpoint the junction will switch to the voltage state consistent with thecircuit load resistor R and the device's own voltage-current curve J,determined by the physics and manufacturing art.

FIG. 3 illustrates a Josephson junction device 29 known in the priorart, in which switching occurs by imposing a magnetic field into ajunction via a control line placed above it. The current I to becontrolled is carried through a first layer of superconducting material30 on a substrate 31. A thin film of insulator 32 separates the firstsuperconducting material 30 from a second layer of superconductingmaterial 33. An insulator layer 35 separates layer 33 from a third layerof superconducting material 36. When a control current Ic, passesthrough layer 36, a magnetic field 37 is created at the junction, whichreduces the maximum allowed zero resistance current. Thus, if thedevice's transport current I is greater than the new allowed value, thedevice will switch into the voltage state, similar to as described abovewith regard to FIGS. 1 and 2. The device can be fabricated to switchwith picosecond rise times, with its final voltage state in themillivolts range for presently available materials. The currents thatare switched are most often in the hundreds of microamperes range. Thepower dissipation per unit is in the microwatt range.

The prior art also includes fabrication of Josephson Junctions in whichthe device has the current versus voltage curve represented by FIG. 4,as compared with FIG. 2. This behavior may be acquired by a resistorbeing placed between the electrode and the counter-electrode of thedevice in FIG. 1. Or, equivalently, one may achieve such a “weak link”behavior by fabricating the Josephson device with a conductor betweenthe two electrodes of FIG. 1. It is also well known that such behavioris a standard property of so-called “high temperature” superconductiveJosephson Junctions. The effect of such a device is to provide avoltage, when switched, which is dependent upon the resistors in thecircuit. Nevertheless, the circuits required can still be made from suchjunctions.

If one connects a Josephson junction in parallel with an inductance, theclosed loop forms a Superconducting Quantum Interference Device (SQUID),which is also known in the prior art. Insertion of a second junctioninto this loop, as illustrated in FIG. 5, also produces a SQUID, butwith device properties that are very advantageous in switchingapplications. In particular, if an input current Ig is inserted anddivided between the two junctions, J1 and J2, that zero resistancetransport current can be controlled by introducing magnetic flux intothe closed loop via the control current, Ic. FIG. 6 shows the curve ofallowed zero resistance current, Ig, as a function of the imposedcontrol current, Ic. Im represents the maximum gate current Ig as afunction of the control current Ic. In particular, if an input currentIg is inserted, it will be divided into two paths according to the sizeof the inductors L1, and L2 and the maximum critical currents of J1 andJ2, as well as by the control line current Ic, which is magneticallycoupled to the loop. FIG. 6 represents the joint values of Ig and Ic,for which current Ig can be transported through the loop with zeroresistance. This region is represented by the shaded area. Joint valuesof Ig and Ic, which are above this area, will result in non-zero voltagetransport of Ig. A control line can thus be used to change the maximumzero resistance current of a two terminal Josephson junction, or SQUID.The detailed properties depend upon the inductance, critical currents ofthe device, and insertion point(s) of the currents. (A more detailedexplanation of the structure and operation of the Josephson junction andthe SQUID is found in the IBM Journal of Research and Development, vol.24, No. 2 (March 1980), which is hereby incorporated by reference.)

Superconductive Crossbar Switch

FIG. 7 illustrates a superconductive crossbar switch, in accordance withan embodiment of the present invention. The superconductive crossbarswitch 39 includes at least one cell 41 in a matrix, which are arrangedin rows and columns in accordance with the number of input lines Ii 40and output lines Oi 43. For example, there are N inputs and M outputsfor coupling, such as via or including wired, wireless, or fiberopticconnections, N processors with M memories. The number of inputs andoutputs need not be equal. In one embodiment of the present invention,the superconductive crossbar switch 39 is extendable to accommodatelarge numbers of processors and memories. Thus, for example, the modulecan easily be extended from a 32 input×32 output to a 1024 input×1024output configuration, as is further described below.

Each input port connects to a row of cells 41 via an input line Ii 40.Each cell 41 includes a connecting circuit 44, which connects the inputline Ii to a selected output line Oi for bidirectionally transmittingdata therebetween. The connecting circuit includes a firstsuperconductive device 42, which has zero-resistance. A first controlsignal applied to a first terminal 45 controls the first superconductivedevice 42 externally on command, for controlling operation of thesuperconductive crossbar switch 39. In one embodiment, the first controlsignal comprises an electrical current.

Each cell 41 also includes a retaining and releasing circuit forretaining (i.e., clamping) and releasing the operation of the firstsuperconductive device 42. The retaining and releasing circuit includesa second superconductive device 46 and a second control signal,delivered through a clamp line 49 at a second terminal 47, forcontrolling the second superconductive device 46 and the devices 46 ofthe cells 41 in the same column of cells 41, as shown in FIG. 7.

The first and second superconductive devices 42 and 46 can also beaddressed by optical illumination, in another embodiment of the presentinvention. For example, if the first superconductive device 42 isoptically illuminated, the switch cell connection from input to outputwill be maintained for the duration of the optical signal. In effect,the optical beam has “enabled” the desired connection. If the secondsuperconductive device 46 is addressed by the optical beam, the currentwill be steered into the control line for the first superconductivedevice 42. Alternatively, an electron beam could be used instead of anoptical beam.

When the cells 41 are arranged in a matrix as shown in FIG. 7, eachinput line Ii 40 is coupled to a cell 41 (e.g., a row of cells), therebyto define a matrix of cells.

Method of Using the Superconductive Crossbar Switch

FIGS. 8 and 9 illustrate use of the superconductive crossbar switch 39,in accordance with an embodiment of the present invention. Referring toFIG. 8, the processors and memories coupled to the input lines 40(Ii=I4, I5, I6) and output lines 43 (Oi=O8, O9, O10), respectively, neednot be synchronously clocked, but instead may be run independently. Theoperation will be described for the example of a 32 input×32 outputcrossbar chip organized as shown in FIG. 8, but it should be understoodthat any number of inputs 40 and outputs 43 may be provided. In thisexample, each of the 32 input lines from the 32 processors transmits aserial bit stream. The first serial bit word, or part of it, from aprocessor (or other source), contains the address of the specific memoryline which the processor is attempting to acquire. In addition, theaddress bits are followed by a “FLAG” bit, a “one.” This first wordcarrying the destination address and the FLAG bit is input to therequesting processor's data line. The decoder selects the appropriate1st control line (45 a) and powers it, thereby permitting the FLAG bitto proceed to the output line.

The initial state of each cell is a zero current condition in the firstaddress terminals 45 a, 45 b, 45 c, and 45 d, corresponding to the firstterminal 45 in FIG. 7. As there is no current in the address lines, allthe devices 42 a, 42 b, 42 c, and 42 d will short the processor pulseson input lines 40 to ground and therefore no output is observed atoutput lines 43.

If now the processor coupled to input line I4 attempts to access thememory coupled to output line O8, the process of FIG. 9 is followed. Theprocessor decoder selects the address line for the output line O8,contained in the processor's request word (step 905 of FIG. 9). Afterthe address line is found (decoded), it is determined if there is acontrol current for the address line (step 910 of FIG. 9).

If there is a control current (step 910 of FIG. 9), a decoder current isimpressed at terminal 45 a, which depresses the zero resistance currentthreshold of superconductive device 42 a, thereby allowing input pulsesto be transferred across the superconductive device 42 a (step 915 ofFIG. 9). Subsequent pulses from the processor or input line I4 are thenfed into the output line O8, and thus, for example, into a summingcircuit 50.

If there is no control current for the address line (step 910 of FIG.9), the input pulses on input line I5 are not transferred to output lineO8 (step 920 of FIG. 9), but are shorted to ground by thesuperconductive device 42 b, as shown in FIG. 8. Thus, the input pulsesfrom another processor do not interfere with the data pulses from inputline I4 on output line O8.

Correspondingly, if, for example, input line I5 seeks to send data tooutput line O9, then a current is impressed at terminal 45 d by theprocessor decoder and the input data pulse stream is then imposed uponoutput line O9, with no interference from the processor coupled to inputline I4 because its control line 45 b is not driven.

Superconductive Crossbar Switch Coupled to Summing Device

FIGS. 10 and 11 illustrate use of an example superconductive crossbarswitch 39 coupled to a summing device 68, in accordance with anembodiment of the present invention. Referring to FIG. 10, each cell 41is similar to the cells 41 shown in FIG. 8. In addition, each outputline 43 is coupled to a summing device 68 containing a thirdsuperconductive device 51 controlled by the control line 65. An inputdriver circuit 52 couples each input line to its correspondingprocessor.

FIG. 11 illustrates an exemplary process for using the superconductivecrossbar switch 39, coupled to a summing device 68, as shown in FIG. 10.In FIG. 10, pulses a from the processor drive additional superconductivedevices 55 into the voltage state and thereby impress a voltage on theinput line 40 (step 1105 of FIG. 11), which is coupled to all the rowcells accessed by that processor. The impressed voltage causes a currentto flow through the resistor 57 to be shorted to ground via the firstsuperconductive device 42 (step 1110 of FIG. 11).

It is determined if the control signal provided at terminal 45 ispowered (step 1115 of FIG. 11). If yes, that control signal can be madesufficient to reduce the critical current through first superconductivedevice 42, such that it exhibits a “gap” voltage (step 1120 of FIG. 11).The pulse current passing through the first superconductive device 42will exceed the maximum zero resistance current and the firstsuperconductive device 42 will switch into the voltage state, therebyimpressing its “gap” voltage upon the cell tie point between resistors57 and 62.

If the control signal is not powered (step 1115 of FIG. 11), thesuperconductive device 42 may be operated such that it transfers to aresistive state, or the superconductive device 42 itself may befabricated such that it does not exhibit a “gap” voltage (step 1125 ofFIG. 11). This voltage will cause a current to flow through resistor 62down to the output line 63 through control 65 and additionalsuperconductive devices 66. This current will be insufficient to switchadditional superconductive devices 66, and therefore, since control 65is of very low inductance, the voltage across control 65 and additionalsuperconductive devices 66 will be very small and will decay veryrapidly, such that the current through resistor 62 will predominately gothrough control 65 and only a negligible amount will pass throughresistor 67, and eventually all current will pass through control 65 andadditional superconductive devices 66.

The current through control 65 depresses the maximum allowed zeroresistance current of superconductive device 51, which then triggers andproduces a signal for transfer to the memory circuits (step 1130 of FIG.11). In an alternative embodiment, other equivalent sensing circuits maybe used instead. The pulse sensed by the memory circuit is inverted,amplified, and fed back via terminal 70 (step 1135 of FIG. 11) after anappropriate delay, with sufficient current to exceed the allowed maximumcurrent through superconductive devices 66 and thereby impose a voltageon the output line 43, which will cause current to flow throughresistors 62 and 67. However, only superconductive device 42 has asuppressed maximum current, and therefore only line 56 will experience acurrent back into control 71 via resistor 57; input line 72 will not. Asbefore, control 71 will control superconductive device 75 and thecurrent through superconductive devices 55 will be too small to switchsuperconductive devices 55 into the voltage state. The input pulse awill be returned as an ‘acknowledge’ pulse t only to the processor 61,which generated pulse a (step 1140 of FIG. 11), and to no other,provided that the selected cell 41 is the only one energized. Thisreturn path is also valid for transfers of data from memory back to theprocessor 61.

Superconductive Crossbar Switch with Summing Devices

With reference to FIG. 12, there is shown a crossbar switch 39 having anumber of summing devices 78, represented in this embodiment byamplifiers M_(i), coupled to each output line 43 (e.g., O₃, O₉, O₁₀).The summing amplifier M₉ is coupled to output line O₉, and so on. Thesumming devices 78 are operable for summing the output voltages of thecells coupled to the respective output line O_(i). Summing the inputvoltages in this manner enables the crossbar switch to accommodate aplurality of inputs and thus renders the matrix extendable in numbers ofinputs and outputs. This comes about because the input terminal of theamplifier is summed to zero voltage, thereby producing no crosstalk fromthe selected processor to the other processors.

Superconductive Crossbar Switch with Additional Junction and ControlLine

In order to prevent interference by other processors after an outputline has been acquired, an additional junction and control line isprovided as is illustrated in FIG. 13. The operation of this device willalso be described below with reference to FIGS. 14 and 15. In thecrossbar's initial state, current is applied to clamp line C₈, therebydepressing the maximum zero resistance current of superconductive device46 a (step 1405 of FIG. 14). When terminal 45 a is activated, currentwill be caused to flow through inductor 106 and control line 107,because the critical current of superconductive device 46 a has beenreduced to below the imposed decoder current level. This will occurbecause the clamp current C suppresses the maximum zero resistancecurrent of device 46 a.

With respect to cell 41 b, current at terminal 45 b will initially flowinto inductor 108 because the inductance of inductor 108 is required tobe lower than the inductance of inductor 106 (step 1410 of FIG. 14).However, since superconductive device 46 a has its maximum zeroresistance current reduced because of the signal imposed at C₈,superconductive device 46 a will switch to the voltage state, and allthe current imposed on terminal 45 b will be directed through inductor106 and control line 107.

After the decoder has applied its current at terminal 45 b, a flag pulseor set of pulses is inserted into the processor datastream at I₄ (step1415 of FIG. 14). These pulses would normally immediately follow thosethat select the address. When these flag pulses are detected on theoutput line O₈ for the cell, the CLAMP current on C₈ will be dropped(step 1420 of FIG. 14). Now, if decoder power to terminal 45 b isremoved, the flux stored in inductor 106 will be maintained by acirculating current in the loop comprising inductors 106, 108 and device46 a. This action of dropping the clamp signal succeeds in not onlyretaining the usage of the output line in cell 41 a after the decoder ispowered down, but it also prohibits interference by other requesters forthe same output line (e.g., in cell 41 c).

With reference to cell 45 c of FIG. 13, the initial state has the CLAMPline C₈ energized, similar to as described above with regard to FIG. 7.Removal of the CLAMP current at C₈ causes the critical current of device46 a to no longer be depressed (step 1425 of FIG. 14). Decoder powerapplied to terminal 45 c, will then flow predominately through inductor111, which is required to have much smaller inductance than theinductance of inductor 112.

The resulting current through inductor 112, and thus control line 113,will be insufficient to depress the critical current of device 116enough for it to switch when data current flows through resistor 117.This, in effect, prevents interference by the processor (step 1430 ofFIG. 14) coupled to line I₅, with the output line O₈ already in use. Byextension, this operation will hold for all late requesters for anoutput line.

FIG. 15 summarizes the above described behavior. Processor 1 is shownhaving powered its decoder output, thereby permitting its flag bit to besent to the SENSE circuits. At a later time, this causes the CLAMP to bedropped at time C from OPEN to CLAMPED at the cell location. Processor 2thus is unable to insert its flag pulse onto the output line. Finally,the “acknowledge” return pulse is received by only processor 1, asprocessor 2 connection is not enabled.

Contention Situation

If two processors request the same memory line at the “same time,” acontention situation occurs. For example, in FIG. 16, if the addresslines 45 b and 45 d are “simultaneously” powered, contention will occurbetween the processors coupled via inputs I₄ and I₅ for the memorycoupled to output line O₉. This will cause the memory acquisition to“flag” bits from both the processors coupled to I₄ and I₅, and thus todrive the output line at the same time. This will produce two units ofcurrent in the control line 91, which triggers the “contention” sensor92. Detection of this event will cause the support electronics to ignorethe SENSE signal and to keep the CLAMP line on current HIGH. Thisfunction may also be provided by cryogenic circuitry. No return“acknowledge” pulse is sent, thereby, by its absence, informing therequesting sources of their failure to acquire the requested outputline.

Situation Where Two Processors Have Requested Memory

FIG. 17 depicts the situation wherein processors 1 and 2 have requestedthe memory at the same time. In that event, the clamp line is notdropped at C, the crossbar cells on that memory line stay available, andno “acknowledge” pulse is returned to the requesters. This silenceadvises them to retry. If processor 2 requests the memory line at a timebetween a and C, the electronics can still keep CLAMP high, withhold“acknowledge,” and thereby maintain availability to other requesters.This may be done at cryogenic temperature or at room temperature.

Example of 128×128 Switch

FIG. 18 shows an example of a 128 input×128 output crossbar switchembodying the features of the present invention. In this example, 64processors 126-126 are coupled to a processor glue chip 127 and 64memories 128-128 are each coupled to a memory glue chip 131. There are64 more processors 136-136 coupled to a second processor glue chip 137and an additional 64 memories 132-132 coupled to a second memory gluechip 133. Connected between these glue chips is a crossbar switch 138essentially comprising a plurality of interconnecting matrices of cellsS1-S16, each of which is a 32×32 crossbar matrix. Each of the 64processors 126-126 is coupled via an input data line 141 to processorglue chip 127, to which each of the 64 processors 126-126 transmitsserial bit data. Processor glue chip 127 outputs and receives that datainto chips S1, S2, S5, S6 for transactions to and from memories 128-128by the 64 processors 126-126. It also outputs and receives the data intochips S9, S10, S13, S14 for transactions to and from memories 132-132 bythe same 64 processors 126-126. Likewise, chips S3, S4, S7, S8 connectprocessors 136-136 to memories 128-128 while chips S11, S12, S15, S16connect processors 136-136 to memories 132-132.

The selection of a memory line by a given processor is accomplished byincluding a destination memory address in that processor's submitteddata word and clocking it via the appropriate input clock line on theproper crossbar chip (i.e., the required input processor andsought-for-output memory line). The destination address may also beintroduced by an external controller and may also be decoded by anexternal decoder.

The return data from the interrogated memory line is fed into thecorresponding memory glue chip as DRIVE, returned in parallel to thecrossbar bank and is transferred to only the activated and lockedprocessor line. From there, it continues to the corresponding processorglue chip and on to the originating processor. Clamping is accomplishedby controlling a separate line (not shown), which disables access of allthe unselected processors to the activated memory line. Contention isseparately detected on the memory glue chip.

Switch Chip

FIG. 19 illustrates an embodiment of a switch chip that interconnects 32input lines to 32 output lines via the previously described matrix ofcells. In this example, each processor is assigned and coupled to itsown decoder, which decodes the destination address that was requested bythat processor and activates the address line of the proper cell in thematrix, as previously described. Such a chip may be replicated topopulate the 128×128 matrix described in FIG. 17.

Example embodiments of the present invention have been described inaccordance with the above advantages. It will be appreciated that theseexamples are merely illustrative of the invention. Many variations andmodifications will be apparent to those skilled in the art.

1. A superconducting crossbar switch, comprising: a plurality of inputlines; a matrix of a plurality of cells, each of the plurality of cellsbeing coupled to one of the plurality of input lines, wherein each cellincludes: a first circuit portion containing a first superconductingswitch; and a second circuit portion, wherein a first signal via thesecond circuit portion triggers the first superconducting switch; aplurality of output lines, each of the plurality of output lines coupledto one of the plurality of cells.
 2. The switch of claim 1, wherein thesecond circuit portion includes a second superconducting switch.
 3. Theswitch of claim 1, wherein the first circuit portion includes a firstresistor in series with the first superconducting switch.
 4. The switchof claim 3, wherein the first superconducting switch is in series with acoupling to a first ground connection.
 5. A superconducting crossbarswitch, comprising: a matrix of a plurality of cells, wherein each cellincludes: a first circuit portion containing a first superconductingswitch; and a second circuit portion, wherein a first signal via thesecond circuit portion triggers the first superconducting switch.
 6. Asuperconducting crossbar switch, comprising: a matrix of a plurality ofcells, wherein each cell includes: a first circuit portion containing afirst superconducting switch; and a second circuit portion, wherein afirst signal via the second circuit portion triggers the firstsuperconducting switch; first and second processor glue chips coupled tothe matrix of a plurality of cells; first and second memory glue chipscoupled to the matrix of a plurality of cells; a first plurality ofprocessors coupled to the first glue chip via a first input data line; asecond plurality of processors coupled to the second glue chip; a firstplurality of memory devices coupled to the first memory glue chip; and asecond plurality of memory devices coupled to the second memory gluechip.